The present invention relates to a solid-state image pickup device and, more particularly, to an output circuit of a solid-state image pickup device wherein a signal charge obtained in each light receiving element through photoelectric conversion is transferred by a charge transferrer and then is outputted after conversion into a corresponding signal voltage.
It is known that for the purpose of reducing the power consumption in a solid-state image pickup device, an output buffer in an output circuit to convert a signal charge into a corresponding signal voltage and to output the same therefrom includes plural cascade-connected stages of source follower circuits, wherein respective supply voltages to the source follower circuits are set to be mutually different in such a manner that the greater the DC current flowing in each source follower circuit, the lower the supply voltage to each of the plural stages of the source follower circuits (see Cited Patent Document 1, for example).
In another known structure of an output buffer in a solid-state image pickup device where source follower circuits are cascade-connected in plural stages, the last-stage source follower circuit consists of a push-pull circuit to thereby reduce the power consumption (see Cited Patent Document 2, for example).
Cited Patent Document 1:
Japanese Patent Specification No. 3351503 (in particular, FIG. 2 and Paragraphs 0037 and 0038)
Cited Patent Document 2:
Japanese Patent Laid-open No. Hei 11-234567 (in particular, FIG. 1 and Paragraph 0021)
In the related art described in Cited Patent Document 1, the output voltage value needs to be lowered in the source follower circuit of each stage, so that it becomes necessary to increase the threshold voltage Vth of a MOS transistor constituting each source follower circuit. Viewing an example of lowering the output voltage value from 15 V or so to 3 V or so, in the case of an output buffer where three stages of source follower circuits are cascade-connected, the gate-source voltage Vgs of the source follower circuit in each stage needs to be set to a high value of 4 V or so. As a result, there arises a problem that the gain of the source follower circuit is lowered due to the substrate bias effect to eventually deteriorate the sensitivity.
Meanwhile according to the related art described in Cited Patent Document 2, in an example of an output buffer where three stages of source follower circuits are cascade-connected similarly to the foregoing case mentioned above, a depletion-mode Pch MOS transistor of which the threshold voltage Vth is 4 V or so needs to be produced for lowering the output voltage value to 4 V or so by the use of the third-stage push-pull circuit. However, since it is difficult to produce a depletion-mode Pch MOS transistor whose threshold voltage Vth is 4 V or so, the output voltage value needs to be lowered from 15 V or so to 3 V or so in the first-stage and second-stage source follower circuits. For this purpose, the gate-source voltage Vgs in each of the first-stage and second-stage source follower circuits needs to be set to 6 V or so, hence raising another problem that the gain of each source follower circuit is further impaired due to the substrate bias effect.